The present disclosure relates to methods and apparatus for providing an interposer for interconnecting semiconductor chips.
Semiconductor packaging technologies have evolved in significant ways over the years. Early on, the approach to package higher complexity semiconductor circuits (and therefore achieving higher functionality and performance in a given package) was to increase the size of a semiconductor chip in two dimensions within the package. As a practical matter, one cannot expand laterally in two dimensions without bound because eventually the design will suffer in terms of power and signal routing complexities, power dissipation problems, performance problems, manufacturing yield problems, etc. In addition, at present there are practical limitations preventing the manufacture of two different semiconductor fabrication processes on a common semiconductor wafer, which also limits the circuit design options available to an artisan.
The above problems associated with expanding a semiconductor chip in two dimensions has led artisans to explore ways of expanding in three dimensions; namely, by expanding vertically. Earlier approaches to vertical expansion of semiconductor chips included chip stacking, such as placing memory chips one atop the other within a single package. While this certainly yielded higher chip density over a single chip package (given a fixed lateral area) there are disadvantages and practical limitations with chip stacking, including power and performance issues, manufacturing yield problems and the like. Another conventional approach to vertical expansion in semiconductor packaging included so-called package-on-package techniques, where a number of separate ball grid array packages are assembled one atop the other (in a stacked arrangement), with a standard interface to route signals between them. The package on package technique also results in higher chip density, although there are inefficiencies with employing separate packages for each semiconductor chip.
Still further approaches to vertical expansion in semiconductor packaging include so-called 2.5-D and 3-D integration, whereby a silicon interposer is employed to interconnect two or more semiconductor chips within a single package. The primary function of the interposer is to provide interconnectivity in such a way that the two or more semiconductor chips may employ high terminal pitch and avoid the need for vias through the semiconductor chips themselves. The technique involves flipping the semiconductor chips over from their usual configuration and orienting the chip substrates up and chip-sides down. The chips are provided with micro-bump terminals (at high pitch), which are connected to corresponding terminals on a top side of the silicon interposer. The opposite, bottom side of the silicon interposer is connected to the package substrate (which is typically organic) by way of suitable terminals, usually Controlled Collapse Chip Connection (C4) joints. The interposer is provided with through silicon vias (TSVs) so that electrical connections may be made from the terminals of the semiconductor ships on the top side of the silicon interposer to the terminals of the package substrate at the bottom side of the silicon interposer. Notably, such a configuration permits the 2.5-D integration of the separate semiconductor chips without requiring TSVs on the active die of the semiconductor chips, which avoids significant complications. The 3-D integration may involve at least one semiconductor chip having TSVs in order to vertically and directly connect two semiconductor chips together and then to connect the combination to the silicon interposer for connection with other semiconductor ships.
While the silicon interposer is a promising and useful technology to achieve vertical integration of semiconductor chips, the conventional interposer technology is not without problems, particularly in terms of mismatches in coefficients of thermal expansion (CTEs) through the stack, including CTE match-up between the silicon interposer and the organic package substrate. Undesirable CTE mismatches may result in failures in the interconnections between the semiconductor chips and the silicon interposer and/or failures in the interconnections between the silicon interposer and the package substrate.
Accordingly, there are needs in the art for new methods and apparatus for providing interposers for interconnecting semiconductor chips.